1. Field of the Invention
The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a method for forming a dielectric layer (such as an inter-layer dielectric) suitable to reduce a dielectric constant thereof and/or a method for forming a copper wiring.
2. Description of the Related Art
A semiconductor manufacturing process may be classified into a Front End of the Line (FEOL) process for forming transistors on a semiconductor substrate and a Back End of the Line (BEOL) process for forming wiring layers.
A wiring technique is a technique of embodying a path of power supply and signal transmission circuits by connecting separate transistors to each other in a semiconductor integrated circuit.
A resistance R of a metal wiring and a capacitance C of an inter-layer dielectric cause a RC delay in a semiconductor device. Accordingly, so as to drive the semiconductor device at high speed, the resistance R of a metal wiring and the capacitance C of an inter-layer dielectric should be reduced.
In recent years, in order to improve the RC delay in the semiconductor device, the resistance of the metal wiring has been lowered by using copper (Cu), which has a low specific resistance, as a metal wiring of the semiconductor device. In addition, an insulator layer having a low dielectric constant has been used to reduce parasitic capacitances between metal wirings.
FIG. 1 is a cross-sectional view showing an inter-layer dielectric having a low dielectric constant according to the related art. FIG. 2 is a cross-sectional view showing a damascene structure for forming a copper wiring according to the related art.
Referring to FIG. 1, to form a wiring using a damascene process, an insulating layer has a structure in which an etch stop layer 4, an inter-layer dielectric 6 having a low dielectric constant, and an oxide layer 8 are sequentially formed on a lower copper wiring 2.
Next, the oxide layer 8 and the inter-layer dielectric 6 are selectively etched to form a via hole 11 and a trench 13 as shown in FIG. 2, and a copper wiring is then formed in the via hole 11 and the trench 13.
As described earlier, when a low dielectric layer is used as the inter-layer dielectric, the dielectric constant thereof may be reduced to a value of less than approximately 3.6, thereby reducing the RC delay in a wiring of the semiconductor device. However, recently, in order to further reduce the RC delay, the development of technology for further reducing a dielectric constant of the inter-layer dielectric has been in progress.